The present disclosure relates to layouts of semiconductor devices, and specifically relates to techniques effective for reducing an optical proximity effect.
In a general process for fabricating a semiconductor integrated circuit, a photolithography step including application of a resist, light exposure, and development, an etching step for patterning elements using a resist mask, and a step of removing the resist are repeated to form an integrated circuit on a semiconductor substrate. If pattern dimensions are equal to or smaller than the wavelength of the exposure light in the photolithography step, differences between the designed layout dimensions and the pattern dimensions formed on the semiconductor substrate become large due to an optical proximity effect of the diffracted light.
In a semiconductor integrated circuit, the gate length of a transistor is an important factor which influences the performance of the semiconductor integrated circuit. Thus, if variations in gate dimensions occur in the fabrication process, it significantly affects the operational performance of the semiconductor integrated circuit.
For this reason, with the progression of miniaturization, it becomes essential to correct the variations in pattern dimensions caused by the optical proximity effect, when patterns such as a wire are drawn and exposed to light in the fabrication process of the semiconductor integrated circuit. Examples of the technique for correcting the optical proximity effect include an optical proximity effect correction (OPC). The OPC is a technique in which an amount of change in the gate length due to an optical proximity effect is predicted from a distance between a gate and its adjacent gate pattern, and the mask measurements of the photoresist for forming the gate are corrected beforehand to compensate the predicted amount of change, thereby maintaining the finished measurements of the gate length after light exposure constant.
However, in conventional techniques, gate patterns have not been standardized and there have been various gate lengths and gate spaces on the entire chip. Thus, problems such as an increase in turn around time (TAT) or an increase in amount of processing are caused by the gate mask correction by OPC.